View HT16L21_6257734.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.00 1 november 16, 2011 rev. 0.00 pb november 16, 2011 HT16L21 ram mapping 324 lcd driver feature ? logic operating voltage: 1.8v~5.5v ? lcd operating voltage (v lcd ): 2.4v~6.0v ? external v lcd pin to supply lcd operating voltage ? internal 32khz rc oscillator ? bias: 1/2 or 1/3; duty:1/4 ? internal lcd bias generation with voltage-follower buffers ? integrated regulator to adjust lcd operating voltage: 3.0v, 3.2v, 3.3v, 3.4v, 4.4v, 4.5v, 4.6v, 5.0v ? integrated led driver ? support i 2 c or spi 3-wire serial interface controlled by ifs pin ? four selectable lcd frame frequencies: 64hz or 85.3hz or 128hz or 170.6hz ? 324 bits ram for display data storage ? max. 324 pixel: 32 segments and 4 commons ? support two driver output mode segment/led on seg24~seg31/led7~led0 ? versatile blinking modes: off, 0.5hz, 1hz, 2hz ? r/w address auto increment ? low power consumption ? manufactured in silicon gate cmos process ? package types: 44lqfp applications ? leisure products ? games ? telephone display ? audio combo display ? video player display ? kitchen appliance display ? measurement equipment display ? household appliance ? consumer electronics general description the HT16L21 device is a memory mapping and multi-function lcd controller/driver. the display segments of the device are 128 patterns (32 segments and 4 commons) display. it can also support led drive outputs on certain segment pins. the software configuration feature of the HT16L21 device makes it suitable for multiple lcd applications including lcd modules and display subsystems. the HT16L21 device communicates with most microprocessors/microcontrollers via a two-wire bidirectional i 2 c or a three-wire spi interface. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 2 november 16, 2011 HT16L21 block diagram lcd voltage selector column /segment driver output segment /led driver output display ram timing generator i2c or 3-wire controller com0 com3 seg0 seg23 rstb vlcd sda/dio scl/clk internal rc oscillator power_on reset regulator r op1 ifs csb seg31/led0 seg24/led7 lcd bias generator r r op0 9(elw vss vdd vdd voltage supported range vlcd voltage supported range www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 3 november 16, 2011 HT16L21 pin assignment 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 2 3 4 5 6 7 8 9 1 0 1 1 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 csb clk/scl HT16L21 44 lqfp dio/sda rstb vdd vlcd com0 com1 com2 com3 seg0 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 led7/seg24 led6/seg25 led5/seg26 led4/seg27 led3/seg28 led2/seg29 led1/seg30 led0/seg31 vss ifs pin description pin name type description sda/dio i/o serial data input/output pin serial data (sda) input/output for 2-wire i 2 c interface is an nmos open drain structure. serial data (dio) input/output for 3-wire spi interface is a cmos input/output structure. scl/clk i serial clock input pin serial data (scl) is clock input for 2-wire i 2 c interface. serial data (clk) is clock input for 3-wire spi interface csb i chip select pin this pin is available for 3-wire spi interface and not used for i 2 c interface. ifs i communication interface select pin this pin is used to select the communication interface. when this pin is connected to v dd , the device communicates with mcu or microprocessors via a 2-wire i 2 c interface. when this pin is connected to v ss , the device communicates with mcu or microprocessors using a 3-wire spi interface. com0~com3 o lcd common outputs seg0~seg23 o lcd segment outputs seg24/led7~seg31/led0 o lcd segment/led multiplexed driver outputs rstb i reset input pin 1. this pin is used to initialize all the internal registers and the commands pin. 2. if use internal power on reset circuit only, the rstb pin must be connected to v dd . vdd positive power supply vss negative power supply, ground. vlcd lcd power supply pin www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 4 november 16, 2011 HT16L21 approximate internal connections vdd vss scl, sda (for schmit trigger type) vselect-on vselect-off com0~com4; seg0~seg31 vdd vss ifs, vss led0~7 csb, clk (for schmit trigger type) vdd vss vss dio (for schmitt trigger type) rstb absolute maximum ratings supply voltage ...................................................................................................................... v ss ?0.3v to v ss +6.6v input voltage ........................................................................................................................ v ss ? 0.3v to v dd +0.3v led driver output current (total) ..................................................................................................................... 88ma storage temperature ....................................................................................................................... -55 c to + 150c operating temperature ..................................................................................................................... -40 c to + 85 c note: these are stress ratings only. stresses exceeding the range specifed under "absolute maximum ratings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 5 november 16, 2011 HT16L21 timing diagrams i 2 c timing sda scl t f t hd:sta t low t r t hd:dat t su:dat t high t su:sta t hd:sta s sr t sp t su:sto p t buf s t aa sda out spi timing t csw t csh t ds t hs t cw t cw t sys dio (input ) clk csb 10% t csl t pd dio (output ) 90% 90% 90% 90% 90% 90% 90% 90% 90% 90% 10% 10% 10% 10% 10% 10% 10% 10% v dd v ss v dd v ss v dd v ss v dd v ss 10% t pd reset timing vdd data transfer t pof t sr 50% 0.9v 0.9v t rson t rsoff 50% 80% t rw t rsoff t rsoff rstb 50% 50% 50% 50% 50% note: 1. if the conditions of reset timing are not satisfed in power on/off sequence, the internal power on reset (por) circuit will not operate normally. 2. if the v dd drops lower than the minimum operating voltage during operating, the conditions of power on reset timing must also be satisfed. that is the v dd drop to 0.9v and keep at 0.9v for 10ms (min.) before rising to the normal operating voltage. 3. data transfers on the i 2 c interface or spi 3-wire serial interface should at least be delayed for 1ms after the power-on sequence to ensure that the reset operation is complete . www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 6 november 16, 2011 HT16L21 d.c. characteristics v ss =0v; v dd =1.8v to 5.5v; ta=-40~85c symbol parameter test condition min. typ. max. unit v dd condition v dd operating voltage 1.8 5.5 v v lcd lcd operating voltage 2.4 6.0 v v ih input high voltage csb, clk, dio, rstb 0.7v dd v dd v v il input low voltage csb, clk, dio, rstb 0 0.3v dd v i il input leakage current v i n =v ss or v dd -1 1 a i o h high level output current 2.0v v o h =0. 9 v dd for dio pin -2 ma 3.3v -6 ma 5.0v -12 ma i ol l ow level output current 2.0v v ol =0.4v for sda /dio pin 3 ma 3.3v 6 ma 5.0v 9 ma i dd operating current 2.0v no load , f lcd = 64 hz, 1/3bias, lcd display on , internal s ystem oscillator on , vlcd pin input voltage =5v , disable integrated regulator 1 2.5 a 3.3v 2 5 a 5.0v 4 10 a i lcd1 operating current 2.0v no load, f lcd = 64 hz, 1/3bias, lcd display on , internal s ystem oscillator on , vlcd pin input voltage =5v , disable integrated regulator 25 40 a i lcd2 operating current 2.0v no load, f lcd = 64 hz, 1/3bias, lcd display on , internal s ystem oscillator on , vlcd pin input voltage =5 .5 v , r egulator output is set to 5v 30 52 a i stb 1 standby current for v dd 3.3v no load, 1/3bias, lcd display off , internal s ystem oscillator o ff 1 a 5.0v vlcd pin input voltage =5v, disable integrated regulator 2 a i stb 2 standby current for v lcd 3.3v no load, 1/3bias, lcd display off , internal s ystem oscillator o ff 1 a 5.0v vlcd pin input voltage =5v, disable integrated regulator 2 a v reg r egulator output vlcd pin input voltage =5 .5 v , r egulator output is set to 4.5v, ta=-40 c ~85 c 4.35 4.5 4.65 v vlcd pin input voltage =5 .5 v , r egulator output is set to 4.5v, ta=25 c 4.42 4.5 4.58 v i o l 1 lcd common sink current v lcd =3.3v, v ol =0.3 3 v , disable integrated regulator 250 400 a v lcd =5v, v ol =0.5v , disable integrated regulator 500 800 a i oh 1 lcd common source current v lcd =3.3v, v oh =2. 9 7v , disable integrated regulator - 140 - 230 a v lcd =5v, v oh =4.5v , disable integrated regulator - 300 - 500 a i ol 2 lcd segment sink current v lcd =3.3v, v ol =0.3 3 v , disable integrated regulator 250 400 a v lcd =5v, v ol =0.5v , disable integrated regulator 500 800 a i oh 2 lcd segment source current v lcd =3.3v, v oh =2. 9 7v , disable integrated regulator - 140 - 230 a v lcd =5v, v oh =4.5v , disable integrated regulator - 300 - 500 a www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 7 november 16, 2011 HT16L21 symbol parameter test condition min. typ. max. unit v dd condition i ol3 led sink current v lcd =3.3v, v o l = 1 v , when sp1 bit is set to 1 10 ma v lcd =5.0v, v o l = 2 v , when sp1 bit is set to 1 20 ma n ote: 1. p lease use the integrated regulator when the regulator output voltage is less than ( v lcd ? 0.5v) . 2. if 8 leds turn on at the same time, total current of led drivers can not be allowed more than 80ma. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 8 november 16, 2011 HT16L21 a.c. characteristics unless otherwise specifed, v dd =1.8 to 5.5v; v ss = 0 v; ta =-40~85c symbol parameter test condition min. typ. max. unit v dd condition f lcd1 lcd frame frequency ta=25 c , v dd =3.3v frame frequency is set to 64hz 57.6 64 70.4 hz frame frequency is set to 85.3hz 76 85.3 94.0 frame frequency is set to 128hz 115.2 128 140.8 frame frequency is set to170.6hz 152 170.6 188.0 f lcd2 ta=-40~85 c , v dd =2.5~5.5v frame frequency is set to 64hz 51.2 64 83.0 hz frame frequency is set to 85.3hz 68 85.3 111 frame frequency is set to 128hz 102.4 128 166 frame frequency is set to170.6hz 136 170.6 222 f lcd3 ta=-40~85c v dd =1.8~2.5v frame frequency is set to 64hz 45.0 64 hz frame frequency is set to 85.3hz 59.0 85.3 frame frequency is set to 128hz 90.0 128 frame frequency is set to170.6hz 118.0 170.6 t sr v dd slew rate 3.3 0.05 v/ms 5.0 t pof v dd off times 3.3 v dd drop down to 0 .9 v 1 0 ms 5.0 t rson rstb input time 3.3 w hen rstb signal is externally input from a microcontroller etc. 250 ns 5.0 3.3 r=100k and c=0.1f (see application circuit) 100 ms 5.0 t rw rstb pulse width 3.3 w hen rstb signal is externally input from a microcontroller etc. 400 ns 5.0 t rsoff wait time for data transfers 3.3 2-wire i 2 c or 3-wire spi interface 1 ms 5.0 note: f lcd = 1/t lcd www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 9 november 16, 2011 HT16L21 a.c. characteristics C i 2 c interface unless otherwise specifed, v ss =0v; v dd =1.8v to 5.5v; ta=-40~85c symbol parameter condition v dd =1.8v to 5.5v v dd =3.0v to 5.5v unit min. max. min. max. f scl clock frequency 100 400 khz t buf bus free time time in which the bus must be free before a new transmission can start 4.7 1.3 s t hd: sta start condition hold time after this period, the frst clock pulse is generated 4 0.6 s t low scl low time 4.7 1.3 s t high scl high time 4 0.6 s t su: sta start condition setup time only relevant for repeated start condition 4.7 0.6 s t hd: dat data hold time 0 0 ns t su: dat data setup time 250 100 ns t r sda and scl rise time note 1 0.3 s t f sda and scl fall time note 0.3 0.3 s t su: sto stop condition set-up time 4 0.6 s t aa output valid from clock 3.5 0.9 s t sp input filter time constant (sda and scl pins) noise suppression time 20 20 ns note: these parameters are periodically sampled but not 100% tested. a.c. characteristics C spi interface unless otherwise specifed, v ss =0v; v dd =1.8v to 5.5v; ta=-40~85c symbol parameter test condition min. typ. max. unit v dd condition t sys clock cycle time f or w rite data 250 ns f or read data 1000 ns t cw clock pulse width f or w rite data 50 ns f or read data 400 ns t ds data setup time f or w rite data 50 ns t dh data hold time f or w rite data 50 ns t csw h csb pulse width 50 ns t csl csb setup time (csbDclk) f or w rite data 50 ns f or read data 400 ns t csh cs hold time (clkDcsb) 2 s t pd data output delay time (clkDdio) c o =15pf t pd =10% to 90% 350 ns t pd =90% to 10% www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 10 november 16, 2011 HT16L21 lcd frame frequency f lcd is set to 64hz 0 10 20 30 40 50 60 70 80 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 v dd (v) lcd frame frequency (hz) -40 -20 0 25 65 85 lcd frame frequency f lcd is set to 128hz 0 20 40 60 80 100 120 140 160 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 v dd (v) lcd frame frequency (hz) -40 -20 0 25 65 85 lcd frame frequency f lcd is set to 85.3hz 0 10 20 30 40 50 60 70 80 90 100 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 v dd (v) lcd frame frequency (hz) -40 -20 0 25 65 85 lcd frame frequency f lcd is set to 170.6hz 0 20 40 60 80 100 120 140 160 180 200 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 v dd (v) lcd frame frequency (hz) -40 -20 0 25 65 85 characteristics curves C f lcd vs. v dd vs. temperature www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 11 november 16, 2011 HT16L21 functional description power-on reset when the power is applied , t he device is initialized by an internal power-on reset circuit. the status of the internal circuit s after initialization is as follows: ? all common outputs are set to v lcd. ? all segment outputs are set to v lcd . ? the 1 / 3 bias drive mode is selected . ? the system oscillator and the lcd bias generator are off state. ? lcd display is off state. ? i ntegrated regulator is disabled. ? i nternal voltage adjustment function is enabled. ? the segment/l e d shared pin s are set as the segment pin s. ? frame frequency is set to 64hz. ? blinking function is switched off. reset function when the rstb pin is pulled to a low level, a reset operation is executed and it will initialize all functions . the status of the internal circuit s after initialization is as follows: ? all common outputs are set to v lcd. ? all segment outputs are set to v lcd . ? the 1 / 3 bias drive mode is selected . ? the system oscillator and the lcd bias generator are off state. ? lcd display is off state. ? i ntegrated regulator is disabled. ? the segment/l e d shared pin is set as the segment pin . ? frame frequency is set to 64hz. ? blinking function is switched off. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 12 november 16, 2011 HT16L21 display memory C ram structure the display ram is static 324-bits ram which stores the lcd data. logic 1 in the ram bit-map indicates the on state of the corresponding lcd segment; similarly, logic 0 indicates the off state. the contents of the ram data are directly mapped to the lcd data. the frst ram column corresponds to the segments operated with respect to com0. in multiplexed lcd applications the segment data of the second, third and fourth column of the display ram are time-multiplexed with com1, com2 and com3 respectively. the following diagram is a data transfer format for i 2 c or spi interface. d0 msb lsb d1 d2 d3 d4 d5 d6 d7 lcd led0 led1 led2 led3 led4 led5 led6 led7 led lcd display or led output data transfer format for i 2 c or spi interface 324 display mode when the sp1 bit is set to 0 and the sp0 bit is set to 0 or 1, the drive mode is selected as 32 segments by 4 commons. this drive mode is also the default setting after a reset. output com3 com2 com1 com0 output com3 com2 com1 com0 address seg1 seg0 00h seg3 seg2 01h seg5 seg4 02h seg31 seg30 0fh d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 324 display mode 284 display mode when the sp1 bit is set to 1 and the sp0 bit is set to 0, the drive mode is selected as 28 segments by 4 commons together with 4 led driving outputs. output com3 com2 com1 com0 output com3 com2 com1 com0 address seg1 seg0 00h seg3 seg2 01h seg5 seg4 02h seg27 seg26 0dh d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 284 display mode www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 13 november 16, 2011 HT16L21 244 display mode when the sp1 bit is set to 1 and the sp0 bit is set to 1, the drive mode is selected as 24 segments by 4 commons together with 8 led driving outputs. output com3 com2 com1 com0 output com3 com2 com1 com0 address seg1 seg0 00h seg3 seg2 01h seg5 seg4 02h seg23 seg22 0bh d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 244 display mode system oscillator the timing for the internal logic and the lcd drive signals are generated by an internal oscillator. the system clock frequency (f sys ) determines the lcd frame frequency. during initial system power on the system oscillator will be in the stop state. lcd bias generator the lcd supply power can come from the external vlcd pin or the internal regulator output voltage determined using the internal voltage adjustment (iva) setting command. t he device provides an external vlcd pin and also integrates an internal regulator. the lcd voltage may be temperature c ompensated externally through the v oltage supply to the vlcd pin. t he internal regulator can also provide the lcd operating voltage. therefore, t he full-scale lcd voltage (v op ) is obtained from ( v lc d Cv ss ) or ( v reg Cv ss ) . fractional lcd biasing voltages , known as 1/2 or 1/3 bias voltage, are obtained from an internal voltage divider of four series resistors connected between v lcd and v ss . the centre resistor can be switched out of circuit s to provide a 1 /2 bias voltage level confguration . www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 14 november 16, 2011 HT16L21 lcd drive mode waveforms ? when the lcd drive mode is selected as 1/4 duty and 1/2 bias, the waveform and lcd display is shown as follows: seg n+2 seg n+2 v lcd v lcd v ss v ss seg n seg n com0 com0 com1 com1 com2 com2 seg n+3 seg n+3 com3 com3 seg n+1 seg n+1 (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 v lcd v lcd v ss v ss (v lcd +v ss )/2 (v lcd +v ss )/2 state1 (on) state1 (on) state2 (off) state2 (off) lcd segment lcd segment t lcd waveforms for 1/ 4 duty drive mode with1/ 2 bias ( v op =v lcd ?v ss ) n ote: t lcd = 1/f lcd www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 15 november 16, 2011 HT16L21 ? when the lcd drive mode is selected as 1/4 duty and 1/3 bias, the waveform and lcd display is shown as follows: state1 (on) state1 (on) seg n+2 seg n+2 seg n seg n com0 com0 com1 com1 state2 (off) state2 (off) lcd segment lcd segment com2 com2 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 seg n+3 seg n+3 com3 com3 seg n+1 seg n+1 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 t lcd waveforms for 1/ 4 duty drive mode with 1/ 2 bias ( v op =v lcd ?v ss ) n ote: t lcd = 1/f lcd www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 16 november 16, 2011 HT16L21 segment driver outputs the lcd drive section includes 32 segment outputs seg0~seg31 or 24 segment outputs seg0~seg23 which should be connected directly to the lcd panel. the segment output signals are generated in accordance with the multiplexed led signals and with the data resident in the display latch. the unused segment outputs should be left open-circuit when less than 32 or 24 segment outputs are required. column driver outputs the lcd drive section includes 4 column outputs com0~com3 which should be connected directly to the lcd panel. the column output signals are generated in accordance with the selected lcd drive mode. the unused column outputs should be left open-circuit if less than 4 column outputs are required. address pointer the addressing mechanism for the display ram is implemented using the address pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the address pointer by the display data input command. blinking function the device contains versatile blinking capabilities. the whole display can be blinked at frequencies selected by the blinking frequency command. the blinking frequency is a subdivided ratio of the system frequency. the ratio between the system oscillator and blinking frequencies depends on the blinking mode in which the device is operating, as shown in the following table: blinking mode blinking frequency (hz) 0 blink off 1 2 2 1 3 0.5 frame frequency the device provides four frame frequencies selected with frame frequency command known as 64hz, 85.3hz, 128hz and 170.6hz respectively. led function the led pins are nmos-structured output pins. the data for the led output is contained in the led output setting command, starting from the most signifcant bit. when a written data bit for a led pin is set to 1, the corresponding driving led lights up while the led is switched off when the written data bit is 0. the led pins are pin-shared with the lcd segment pins and can be selected using the sp1 and sp0 bits in the drive mode command. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 17 november 16, 2011 HT16L21 i 2 c serial interface i 2 c operation the device supports i 2 c serial interface . the i 2 c bus is for bidirectional, two-line communication between different ics or modules. t he two lines are a serial data line, sda, and a serial clock line, scl. both lines are connected to the positive supply via pull-up resistors with a typical value of 4.7k. when the bus is free, both lines are high. d evices connected to the bus must have open-drain or open-collector outputs to implement a wired- or function. data transfer is initiated only when the bus is not busy. data validity the data on the sda line must be stable during the high period of the serial clock. the high or low state of the data line can only change when the clock signal on the scl line is low as shown in the diagram. sda scl data line stable; data valid change of data allowed start and stop conditions ? a high to low transition on the sda line while scl is high defnes a start condition. ? a low to high transition on the sda line while scl is high defnes a stop condition. ? start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. ? the bus stays busy if a repeated start (sr) is generated instead of a stop condition. in some respects, the start(s) and repeated start (sr) conditions are functionally identical. p s sda scl sda scl start condition stop condition byte format every byte put on the sda line must be 8-bit long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most signifcant bit, msb, frst. s or sr p or sr sda scl 1 2 7 8 9 ack 1 2 3-8 9 ack p sr www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 18 november 16, 2011 HT16L21 acknowledge ? each bytes of eight bits is followed by one acknowledge bit. t his acknowledge bit is a low level placed on the bus by the receiver. t he master generates an extra acknowledge related clock pulse. ? a slave receiver which is addressed must generate an acknowledge, ack, after the reception of each byte. ? t he device that acknowledges must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. ? a master receiver must signal an end of data to the slave by generating a not-acknowledge, nack, bit on the last byte that has been clocked out of the slave. i n this case, the master receiver must leave the data line high during the 9 th pulse to not acknowledge. t he master will generate a stop or repeated start condition . s 1 2 7 8 9 clock pulse for acknowledgement data output by transmitter data outptu by receiver scl from master acknowledge not acknowledge start condition slave addressing ? the slave address byte is the frst byte received following the start condition form the master device. the frst seven bits of the frst byte make up the slave address. the eighth bit defnes a read or write operation to be performed. when the r/ w bit is 1, then a read operation is selected. a 0 selects a write operation. ? the HT16L21 device address bits are 0111000. when an address byte is sent, the device compares the frst seven bits after the start condition. if they match, the device outputs an acknowledge on the sda line. slave address 0 1 1 1 0 0 0 r/w msb lsb www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 19 november 16, 2011 HT16L21 i 2 c interface write operation byte write operation ? single command type a single command write operation requires a start condition, a slave address with an r/ w bit, a command byte and a stop condition for a single command write operation. slave address ack write command byte ack s 0 1 1 1 0 0 0 0 1 st bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 p i 2 c s ingle c ommand type write operation ? compound command type a compound command write operation requires a start condition, a slave address with an r/ w bit, a command byte, a command setting byte and a stop condition for a compound command write operation. slave address ack write command byte ack s 0 1 1 1 0 0 0 0 1 st bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 command setting ack p 2 nd bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 i 2 c c ompound c ommand type write operation ? display ram single data byte a display ram data byte write operation requires a start condition, a slave address with an r/ w bit, a display data input command byte, a valid register address byte, a data byte and a stop condition. slave address ack write command byte ack s 0 1 1 1 0 0 0 0 data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 register address byte ack 2 nd 1 st 0 0 0 0 0 0 0 1 a0 a1 a2 a3 x x x x i 2 c d isplay ram s ingle data byte write operation www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 20 november 16, 2011 HT16L21 display ram page write operation after a start condition the slave address with the r/ w bit is placed on the bus followed with a display data input command byte and the specifed display ram register address of which the contents are written to the internal address pointer. the data to be written to the memory will be transmitted next and then the internal address pointer will be incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock pulse. after the internal address point reaches the maximum memory address, the address pointer will be reset to 00h. slave address ack write ack s 0 1 1 1 0 0 0 0 ack 2 nd ack data byte p d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d7 d6 d5 d4 d3 d2 d1 d0 2 nd data ack ack data byte d7 d6 d5 d4 d3 d2 d1 d0 1 st data ack register address byte command byte 1 st 0 0 0 0 0 0 0 1 a0 a1 a2 a3 x x x x i 2 c interface n bytes display ram data write operation sp1 sp0 maximum memory address 0 x 0fh 1 0 0dh 1 1 0bh i 2 c interface display ram read operation in this mode, the master reads the HT16L21 data after setting the slave address. following the r/ w bit (="0") is an acknowledge bit, a command byte and the register address byte which is written to the internal address pointer. after the start address of the read operation has been confgured, another start condition and the slave address transferred on the bus followed by the r/ w bit (="1"). then the msb of the data which was addressed is transmitted frst on the i 2 c bus. the address pointer is only incremented by 1 after the reception of an acknowledge clock. that means that if the device is confgured to transmit the data at the address of a n+1 , the master will read and acknowledge the transferred new data byte and the address pointer is incremented to a n+2 . after the internal address pointer reaches the maximum memory address, the address pointer will be reset to 00h. this cycle of reading consecutive addresses will continue until the master sends a stop condition. ack write ack p slave address s 0 1 1 1 0 0 0 0 data byte nack d7 d6 d5 d4 d3 d2 d1 d0 1 st data data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d7 d6 d5 d4 d3 d2 d1 d0 2 nd data ack ack ack slave address read s 0 1 1 1 0 0 0 1 ack register address byte command byte 1 st 2 nd a0 a1 a2 a3 x x x x 0 0 0 0 0 0 0 1 0 i 2 c interface n bytes display ram data read operation www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 21 november 16, 2011 HT16L21 spi serial interface spi operation the device also includes a 3-wire spi serial interface. the spi operations are described as follows: ? the csb pin is used to activate the data transfer. when the csb pin is at a high level, the spi operation will be reset and stopped. if the csb pin changes state from high to low, data transmission will start. ? the data is transferred from the msb of each byte and is shifted into the shift register on each clk rising edge. ? the input data is automatically latched into the internal register for each 8-bit input data after the csb signal goes low. ? for read operations, the mcu should assert a high pulse on the csb pin to change the data transfer direction from input mode to output mode on the dio pin after sending the command byte and the setting values. if the mcu sets the csb signal to a high level again after receiving the output data, the data direction on the dio pin will be changed into input mode and the read operation will end. ? for a read operation, the data is output on the dio pin at the clk falling edge. ? for display ram data read/write operations using the spi interface, the read/write control bit is contained in the display data input command. refer to the display data input command description for more details. spi interface write operation byte write operation ? single command type a single command write operation is activated by the csb signal going low. the 8-bit command byte is shifted from the msb into the shift register at each clk rising edge. bit7 csb clk dio command byte bit6 bit5 bit4 bit3 bit2 bit1 bit0 spi single command type write operation ? compound command type for a compound command, an 8-bit command byte is frst shifted into the shift register followed by an 8-bit command setting. note that the clk high pulse width, after the command byte has been shifted in, must remain at this level for at least 2s after which the command setting data can be consecutively shifted in. csb clk dio command byte command setting bit7 bit6 bit5 bit4 bit3 bit2 bit1 2 s(min) bit6 bit5 bit4 bit3 bit2 bit1 bit7 bit0 bit0 spi compound command type write operation www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 22 november 16, 2011 HT16L21 ? display ram single data byte the display ram single data write operation consists of a display data input (write) command, a register address and a write data byte. x x x x a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 csb clk dio display data input command byte register address byte data byte 1 0 0 0 0 0 0 2 s(min) 2 s(min) 0 spi display ram single data byte write operation display ram page write operation the display ram page write operation consists of a display data write command, a register address of which the contents are written to the internal address pointer followed by n bytes of written data. the data to be written to the memory will be transmitted next and then the internal address pointer will be automatically incremented by 1 to indicate the next memory address location. after the internal address point reaches the maximum memory address, the address pointer will be reset to 00h. 1 0 x x x x a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 csb clk dio 1 st data display data input command byte register address byte data byte 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d7 2 nd data 3 rd data 2 s(min) 2 s(min) 2 s(min) 2 s(min) data byte data byte d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d0 (n-1) th data 2 s(min) csb clk dio spi interface n bytes display ram data write operation sp1 sp0 maximum memory address 0 x 0fh 1 0 0dh 1 1 0bh www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 23 november 16, 2011 HT16L21 spi interface display ram read operation in this mode, the master reads the device data after sending the display data input command when the csb pin changes state from high to low. following the read/write control bit, which is contained in the display data input command, is the register address byte which is written to the internal address pointer. after the start address of the read operation has been confgured, another csb high pulse is placed on the bus and then the msb of the data which was addressed is transmitted frst on the spi bus. the address pointer is only incremented by 1 after the reception of each data byte. that means that if the device is confgured to transmit the data at the address of a n+1 , the master will read the transferred data byte and the address pointer is incremented to a n+2 . after the internal address pointer reaches the maximum memory address, the address pointer will be reset to 00h. this cycle of reading consecutive addresses will continue until the master pulls the csb line to a high level to terminate the data transfer. 1 1 x x a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 csb clk dio 1 st data display data input command byte register address byte 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d7 2 nd data 3 rd data 2 s(min) 2 s(min) 2 s(min) data byte data byte data byte d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d0 (n-1) th data 2 s(min) csb clk dio x x spi interface n bytes display ram data read operation www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 24 november 16, 2011 HT16L21 command summary software reset command this command is used to initialize the HT16L21 device. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def soft reset command 1 st 1 0 1 0 1 0 1 0 w note: when this software reset command is executed, all the command registers are initialized to the default values. after the reset command is executed, the device will experience an internal initialization for 1ms. normal operation can be executed after the device initialization is complete. during the initialization period, no commands can be executed. if the programmed command is not defned, the function will not be af fected. the status of the internal circuits after initialization is as follows: all segment/common outputs are set to v lcd . the 1/3 bias drive mode is selected. the system oscillator and the lcd bias generator are in an off state. the lcd display is in an off state and the integrated regulator is disabled. the segment/led shared pin is setup as a segment pin. the frame frequency is set to 64hz. the blinking function is switched off. drive mode command function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def drive mode setting command 1 st 1 0 0 0 0 0 1 0 w duty, bias and pin-shared setting 2 nd x x sp1 sp0 x x x bias w 00h note: bit0 bias 0 1/3 bias 1 1/2 bias sp1 sp0 segment/led shared pin selected segment 28~31/led3~0 segment 24~27/led7~4 0 x set as segment pins set as segment pins 1 0 set as led pins set as segment pins 1 1 set as led pins set as led pins power on status: the1/3 bias drive mode is selected and also the segment output pins are selected. if the programmed command is not defned, the function will not be af fected. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 25 november 16, 2011 HT16L21 display data input command this command sends data from mcu to the memory map of the HT16L21 device. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def display data input/output command 1 st 1 0 0 0 0 0 0 0 write operation w 1 0 0 0 0 0 0 1 read operation for 3-wire spi interface used only. r address pointer 2 nd x x x x a3 a2 a1 a0 display data start address of memory map w 00h note: sp1 sp0 maximum memory address 0 x 0fh 1 0 0dh 1 1 0bh power on status: the address is set to 00h. if the programmed command is not defned, the function will not be af fected. system mode command this command controls the internal system oscillator on/off and display on/off. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def system mode setting command 1 st 1 0 0 0 0 1 0 0 w system oscillator and display on/off setting 2 nd x x x x x x s e w 00h note: bit internal system oscillator lcd display s e 0 x off off 1 0 on off 1 1 on on power on status: display off and disable the internal system oscillator. if the programmed command is not defned, the function will not be af fected. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 26 november 16, 2011 HT16L21 frame frequency command this command selects the frame frequency. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def frame frequency command 1 st 1 0 0 0 0 1 1 0 w frame frequency setting 2 nd x x x x x x f1 f0 w 02h note: bit [1:0] frame frequency f1, f0 00 85.3hz 01 170.6hz 10 64hz 11 128hz power on status: frame frequency is set to 64hz. if the programmed command is not defned, the function will not be af fected. blinking frequency command this command defnes the blinking frequency of the display modes. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def blinking frequency command 1 st 1 0 0 0 1 0 0 0 w blinking frequency setting 2 nd x x x x x x bk1 bk0 w 00h note: bit blinking frequency bk1 bk0 0 0 blinking off 0 1 2hz 1 0 1hz 1 1 0.5hz power on status: blinking function is switched off. if the programmed command is not defned, the function will not be af fected. led output command this command defnes the blinking frequency of the display modes. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def led output command 1 st 1 0 0 0 1 1 0 0 w led output data 2 nd x x x x led3 led2 led1 led0 when [sp1:sp0]=10 used w 00h led7 led6 led5 led4 led3 led2 led1 led0 when [sp1:sp0]=11 used note: the led registers and latches are cleared after a new confguration is written into the sp1 and sp0 bits in the drive mode command. if the programmed command is not defned, the function will not be af fected. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 27 november 16, 2011 HT16L21 internal voltage adjustment (iva) setting command the internal voltage (v lcd ) adjustment can provide sixteen kinds of regulator voltage adjustment options by setting the lcd operating voltage adjustment command. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def internal voltage adjustment (iva) setting 1 st 1 0 0 0 1 0 1 0 w internal voltage adjust control 2 nd x x x ve x v2 v1 v0 the ve bit is used to enable or disable the internal regulator adjustment for the lcd voltage. the v3~v0 bits can be used to adjust the v lcd voltage. w 00h note: ve regulator adjustment 0 off C bias voltage is supplied from vlcd pin 1 on C bias voltage is supplied from the internal regulator v2 v1 v0 regulator output voltage (v) 0 0 0 3.0v 0 0 1 3.2v 0 1 0 3.3v 0 1 1 3.4v 1 0 0 4.4v 1 0 1 4.5v 1 1 0 4.6v 1 1 1 5.0v power on status: disable the internal regulator. when the v lcd voltage is lower than 3.5v, it is recommended to disable the internal regulator so that the v lcd voltage is directly connected to the internal bias voltage generator. caution: use the internal regulator when the regulator output voltage rev. 1.00 28 november 16, 2011 HT16L21 operation flow chart access procedures are illustrated below using fowcharts. initialization power on set internal lcd frame frequency set internal lcd bias and segment/led share pin set lcd blinking frequency next processing display data read/write (address setting) start next processing display ram data write address setting display on and enable internal system clock www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 29 november 16, 2011 HT16L21 application circuit i 2 c interface ? [sp1:sp0]=0x (1) rstb pin is connected to a mcu. lcd panel com0~com3 seg0~31 com0~com3 seg0~31 HT16L21 mcu scl sda ifs v dd 4.7k 4.7k v dd vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf (2) rstb pin is connected to external resistor and capacitor. lcd panel com0~com3 seg0~31 com0~com3 seg0~31 HT16L21 mcu scl sda ifs v dd 4.7k 4.7k v dd vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf 0.1uf 100k (3) use internal power on reset circuit only, the rstb pin must be connected to v dd lcd panel com0~com3 seg0~31 com0~com3 seg0~31 HT16L21 mcu scl sda ifs v dd 4.7k 4.7k v dd vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 30 november 16, 2011 HT16L21 ? [sp1:sp0]=10 (1) rstb pin is connected to a mcu. r led *4 led*4 lcd panel com0~com3 seg0~27 com0~com3 seg0~27 HT16L21 mcu scl sda ifs v dd 4.7k 4.7k v dd vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf led0 led1 led2 led3 v lcd (2) rstb pin is connected to external resistor and capacitor. lcd panel com0~com3 seg0~27 com0~com3 seg0~27 HT16L21 mcu scl sda ifs v dd 4.7k 4.7k v dd vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf 0.1uf 100k r led *4 led*4 led0 led1 led2 led3 v lcd (3) use internal power on reset circuit only, the rstb pin must be connected to v dd lcd panel com0~com3 seg0~27 com0~com3 seg0~27 HT16L21 mcu scl sda ifs v dd 4.7k 4.7k v dd vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf r led *4 led*4 led0 led1 led2 led3 v lcd www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 31 november 16, 2011 HT16L21 ? [sp1:sp0]=11 (1) rstb pin is connected to a mcu. r led *8 led*8 lcd panel com0~com3 seg0~23 com0~com3 seg0~23 HT16L21 mcu scl sda ifs 4.7k 4.7k v dd vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf v dd v lcd led0 led1 led2 led3 led4 led5 led6 led7 (2) rstb pin is connected to external resistor and capacitor. r led *8 led*8 lcd panel com0~com3 seg0~23 com0~com3 seg0~23 HT16L21 mcu scl sda ifs 4.7k 4.7k v dd vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf v dd v lcd 0.1uf 100k led0 led1 led2 led3 led4 led5 led6 led7 (3) use internal power on reset circuit only, the rstb pin must be connected to v dd r led *8 led*8 lcd panel com0~com3 seg0~23 com0~com3 seg0~23 HT16L21 mcu scl sda ifs 4.7k 4.7k v dd vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf v dd v lcd led0 led1 led2 led3 led4 led5 led6 led7 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 32 november 16, 2011 HT16L21 spi interface ? [sp1:sp0]=0x (1) rstb pin is connected to a mcu. lcd panel com0~com3 seg0~31 com0~com3 seg0~31 HT16L21 mcu csb dio ifs vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf clk (2) rstb pin is connected to external resistor and capacitor. lcd panel com0~com3 seg0~31 com0~com3 seg0~31 HT16L21 mcu csb dio ifs vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf 0.1uf 100k clk (3) use internal power on reset circuit only, the rstb pin must be connected to v dd lcd panel com0~com3 seg0~31 com0~com3 seg0~31 HT16L21 mcu csb dio ifs vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf clk www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 33 november 16, 2011 HT16L21 ? [sp1:sp0]=10 (1) rstb pin is connected to a mcu. r led *4 led*4 lcd panel com0~com3 seg0~27 com0~com3 seg0~27 HT16L21 mcu scl dio ifs vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf led0 led1 led2 led3 v lcd clk (2) rstb pin is connected to external resistor and capacitor. lcd panel com0~com3 seg0~27 com0~com3 seg0~27 HT16L21 mcu csb dio ifs vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf 0.1uf 100k r led *4 led*4 led0 led1 led2 led3 v lcd clk (3) use internal power on reset circuit only, the rstb pin must be connected to v dd lcd panel com0~com3 seg0~27 com0~com3 seg0~27 HT16L21 mcu csb dio ifs vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf r led *4 led*4 led0 led1 led2 led3 v lcd clk www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 34 november 16, 2011 HT16L21 ? [sp1:sp0]=11 (1) rstb pin is connected to a mcu. r led *8 led*8 lcd panel com0~com3 seg0~23 com0~com3 seg0~23 HT16L21 mcu csb dio ifs vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf v lcd clk led0 led1 led2 led3 led4 led5 led6 led7 (2) rstb pin is connected to external resistor and capacitor. r led *8 led*8 lcd panel com0~com3 seg0~23 com0~com3 seg0~23 HT16L21 mcu csb dio ifs vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf v lcd clk 0.1uf 100k led0 led1 led2 led3 led4 led5 led6 led7 (3) use internal power on reset circuit only, the rstb pin must be connected to v dd r led *8 led*8 lcd panel com0~com3 seg0~23 com0~com3 seg0~23 HT16L21 mcu csb dio ifs vlcd vss vdd rstb v lcd v dd 0.1uf 0.1uf v lcd clk led0 led1 led2 led3 led4 led5 led6 led7 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 35 november 16, 2011 HT16L21 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 44-pin lqfp (10mm10mm) (fp2.0mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.469 D 0.476 b 0.390 D 0.398 c 0.469 D 0.476 d 0.390 D 0.398 e D 0.031 D f D 0.012 D g 0.053 D 0.057 h D D 0.063 i D 0.004 D j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 11.90 D 12.10 b 9.90 D 10.10 c 11.90 D 12.10 d 9.90 D 10.10 e D 0.80 D f D 0.30 D g 1.35 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.20 0 D 7 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.00 36 november 16, 2011 HT16L21 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-5631999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modifcation, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www. holtek.com.tw . www.datasheet.co.kr datasheet pdf - http://www..net/

▲Up To Search▲

Price & Availability of HT16L21

	To Download HT16L21 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .